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#2 (permalink) |
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Another common marketing term attached to SDRAM modules is either "CAS2" or "CAS3". Unfortunately, this is a misnomer; these should be called CL2 or CL3, since they refer to CAS Latency timings (2 clocks vs. 3 clocks). The CAS Latency of a chip is determined by the column access time (tCAC). This is the time it takes to transfer the data to the output buffers from the time the /CAS line is activated.
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#3 (permalink) | |
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Quote:
Since you already explained it, im not going to explain it again, but the lower the better
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#5 (permalink) |
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Theres really not, although the first one may have a higher Cas Latency.
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#6 (permalink) |
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well, memory is required to take a break basically so its 2nanoseconds versus 3 nanoseconds. it doesnt effect overall bandwidth nominally...
they also added 2.5 into some memory modules to add stability but keep some performance. most pre-builts have timings that look something like 3-3-3-8 for ddr and 5-5-5-15 for ddr2... which is very high. like i said, it doesnt matter a whole lot... they just do this for pre-builts because it adds stability and greatly decreases chance of a system crash ever happening in the future.
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