whitch prosser is better ?
- Thread starter homeboy
- Start date
the main differences between Celerons and Pentiums are in the areas of bus speed and L2 cache features. Both Pentium-II's and -III's ship with 512kB of secondary (L2) CPU instruction cache. This allows the CPU to store recently used instructions close by and is responsible for much of their high performance.
The Celerons that Intel first introduced as a low-cost CPU alternative (266 & 300MHz versions) were basically just Pentium-II's without any L2 cache at all. This deficiency really punished Celeron performance when compared to competitive AMD and Cyrix chips. In response, subsequent Celeron versions (300A and up) were provided with 128kB of L2 cache. Though only one-quarter the size of the Pentium cache, it was built to run at the full speed of the respective CPU, rather than at half-speed as in the Pentiums. Due to its higher manufacturing cost and technical issues, the larger Pentium cache memory has always been set to run at only half the speed of the CPU itself. For a full-speed L2 in a Pentium design, you need to get into Intel's (much more expensive) Xeon line.
What Intel plays down-- but nearly everyone knows-- is that the full-speed, quarter-size Celeron cache gives them almost the same performance as the half-speed, full-size cache gives Pentiums. Thus you'll find that, for most applications, Celerons rated at the same MHz will equal or better an equivalent Pentium-II, for a much lower price.
The Celerons that Intel first introduced as a low-cost CPU alternative (266 & 300MHz versions) were basically just Pentium-II's without any L2 cache at all. This deficiency really punished Celeron performance when compared to competitive AMD and Cyrix chips. In response, subsequent Celeron versions (300A and up) were provided with 128kB of L2 cache. Though only one-quarter the size of the Pentium cache, it was built to run at the full speed of the respective CPU, rather than at half-speed as in the Pentiums. Due to its higher manufacturing cost and technical issues, the larger Pentium cache memory has always been set to run at only half the speed of the CPU itself. For a full-speed L2 in a Pentium design, you need to get into Intel's (much more expensive) Xeon line.
What Intel plays down-- but nearly everyone knows-- is that the full-speed, quarter-size Celeron cache gives them almost the same performance as the half-speed, full-size cache gives Pentiums. Thus you'll find that, for most applications, Celerons rated at the same MHz will equal or better an equivalent Pentium-II, for a much lower price.
homeboy said:
hmm how to say this 500mhz cel vs p2 yes, 500mhz cel vs p3...uh no. I think you have your facts reversed.omsairam said:
the celeron and p3 will perform similarly but the p3 is faster, although not noticably in all applications. The big differnces are bus speed and cache size. P3s run at 100 and 133mhz where the celerons run at 66mhzIntel April 2000 said:
I should probably pre-empt the argument that 4-way is faster than 8-way set associative by explaining what 4/8-way set associative cache is.
A set associative cache divides the cache into various sections, referred to as sets, with each set containing a number of cache lines. With a 4-way set associative L2 cache, each set contains 4 cache lines, and in an 8-way set associative L2 cache, each set contains 8 cache lines.
8-way has an increased hit rate over 4-way which makes it faster as the amount of system RAM increase.
A set associative cache divides the cache into various sections, referred to as sets, with each set containing a number of cache lines. With a 4-way set associative L2 cache, each set contains 4 cache lines, and in an 8-way set associative L2 cache, each set contains 8 cache lines.
8-way has an increased hit rate over 4-way which makes it faster as the amount of system RAM increase.
Naturally.
ASssuming they are both P3 based Celerons (which is most likely the case), the P3 is not more efficient. It's faster but not more efficient. Why (not)? Because they both run off 10-stage pipes.
You need to make a distinction with P3s though. The Coppermines had on-die L2 and the Katmai's didnt. Your statement is also incorrect in that the Coppermine P3s only had 256K while the older Katmai's had 512K
-Celeron Covington's had 0K of L2
-Celeron Mendocino's had 128K of on-die L2
-Celeron II's had 128K of L2 (this is the model Intel refered to by "Celeron" and then later replaced by the P4 version of this chip)
You do? Xeons are expensive because of their scaling capacity....
Very true however in a day an age where all L2 caches operate at full speed, and where the pipelines are getting (ridiculously long), the quarter cache is a major disadvantage
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LOL you beat me to it
While we're knee deep in cache-land, any idea why Intel chose to do inclusive L2 caching? (i.e., L1 is mirrored in L2)
as we were discussing earlier, I suspect it has to do with Intel's higher latencies, where AMD can run exclusive becuase they run 0 clock latency from L2 to L1 (or did in the days the coppermine p3/celerons were around, there may or may not be some latency there now) but that's just a theory
Well from my most recent [according to the proc I have the direct specs on] info
P4B-3.06
L1 Data = 8K, 4way
L1 Trace = 12 word, 8 way
L2 = 256K, 8 way
A64-3500
L1 Data = 64K, 2way
L1 Trace = 64K, 2 way
L2 = 512K, 16 way
I would assume the architecture of the P4C/P4E is just an improvement on the size rather than the multidirectional access? Maybe something to do with HT? Ok now im really speculating....