Cpu question

Clock speed is only one of the factors that determine performance. For example, the P4's us longer pipelines, so the clock speed has to be insanely high for it to travel from one side to the other. The new C2D's use shorter pipelines, so it doesnt have to travel as fast from one side to the other.
 
thats just processor clock speed, you should also consider other factors like RAM, HD etc. to determine PC overall performance
 
Something about Core 2 Duo now using more instructions at once.
From 3 to 4 channels ... or something.
 
As Omega has said, clock speed is not the only consideration. CPUs with different architecture cannot be directly compared. Significantly, modern P4s use a 31 stage pipeline, whereas Core 2 Duos use a 14 stage pipeline.

Plus they can have a much nicer FSB and very nice cache lol. It all adds up.
Pentium Extreme Editions 955 and 965 also feature 1066Mhz bus speed and 2x2MB Cache. Yet the X6800 solidly outperforms the EE 965, despite being clocked 800Mhz slower.

In fact, all of the Pentium D 9xx series feature 2x2MB cache, whereas the Core 2 Duos E6300 and E6400 feature only 2MB total.

You might find CPU101 helpful.
 
basically more pipelines = better
less pipeleines = worse

which is why an 3.0 intel will beat a 2.4 ghz amd because amd cant keep up with the pricessor speeds because there silicon is the silicon intel rejects.
 
basically more pipelines = better
less pipeleines = worse
Yes, but definitely no.

which is why an 3.0 intel will beat a 2.4 ghz amd because amd cant keep up with the pricessor speeds because there silicon is the silicon intel rejects.
Yeah...but then why will a 1.6GHz intel kick a 2.4GHz AMD's butt? Hmmmm? CPU frequencies really have nothing to do with anything nowadays. They are a horrible indicator of performance, and only uneducated people (the ones who buy computers from walmart) compare processor speeds between two totally different brands and architectures. Now jsut stop, totally stop, before you make a bigger fool of yourself.
 
Oh man. I'm sorry guys, but none of you have a grasp on how processor architecture works. I'll try to sum it up quickly.

P4s use a 20 stage pipeline, a Rapid Execution Engine and a Branch Prediction Unit, amongst a bunch of other pizazz.

The reason for the long pipelines was for Intel to be able to achieve a much higher clock. Theoretically the P4 can surpass 5GHz, and even hit 10, which technically would have wiped AMD off the map.

The second reason for the pipelines is that the shorter each pipeline stage is, the fewer transistors, or gates, are needed and the faster the pipeline can move data.

The pipelines are capable of holding 126 instructions on the fly.

The problem is this. Once the instruction enters the pipeline, you have to wait for it to come out the other end to find out whether the instruction was destined for a predicted address. If the program goofed, the entire pipeline has to be emptied and the process has to start all over again. The Branch Prediction Unit is supposed to cut down on "goofs".

Anyways, that's the partial answer to your problem. There is a lot more, but I don't feel like typing all night. That should give you an idea.
 
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