I'm reading about segmentation and paging.
I understand, basically, how to go from a logical address to a physical one that you put on a bus and hand over to a memory controller.
Though, I'm wondering how many clock cycles it takes.
There seem to be quite a few steps in referencing tables and directories and such.
That is, if you want to reach into physical memory and read or write a location, you have to access descriptor tables, page directories, and page tables all of which are located in physical memory themselves.
So, one attempt at a memory fetch requires 5 or more memory fetches just to grab all the pointers you need to find the address of the memory location that you initially wanted.
So, I'd like to know how many clock cycles it takes to go from a logical address to a physical address if no TLB or paging structure caches are used.
I'd also like to know how many clock cycles it takes to go from a logical address to a physical address if TLB or paging structure caches are used.
I understand, basically, how to go from a logical address to a physical one that you put on a bus and hand over to a memory controller.
Though, I'm wondering how many clock cycles it takes.
There seem to be quite a few steps in referencing tables and directories and such.
That is, if you want to reach into physical memory and read or write a location, you have to access descriptor tables, page directories, and page tables all of which are located in physical memory themselves.
So, one attempt at a memory fetch requires 5 or more memory fetches just to grab all the pointers you need to find the address of the memory location that you initially wanted.
So, I'd like to know how many clock cycles it takes to go from a logical address to a physical address if no TLB or paging structure caches are used.
I'd also like to know how many clock cycles it takes to go from a logical address to a physical address if TLB or paging structure caches are used.
