RAM timings

[The Astroman]

I saw some RAM in this online shop and some people commented they had it in 2/2/2/5 , but I have NO clue what this means...

 

[Cromewell]

normally I don't like THG but this explains it decently http://www6.tomshardware.com/motherboard/20040119/index-02.html

 

[The Astroman]

Right... Any easier to comprehend explanation? Can you tell me like what are good clock times for DDR-SDRAM memory?

 

[Praetor]

Right... Any easier to comprehend explanation?

Any eaiser to comprehend the question?

Can you tell me like what are good clock times for DDR-SDRAM memory?

? good compared to what

 

[Cromewell]

The memory controller selects the active row. But before the row will actually become active so that the columns can be accessed, the controller has to wait for 2-3 cycles - tRCD (RAS-to-CAS delay). Then it sends the actual read command, which is also followed by a delay - the CAS latency. For DDR RAM, CAS latency is 2, 2.5 or 3 cycles. Once this time has lapsed, the data will be sent to the DQ pins. After the data has been retrieved, the controller has to deactivate the row again, which is done within tRP (RAS precharge time).

this says it all, what exactly don't you understand?