AMD 64s dont need northbridge?

There is no Northbridge chip between the CPU and other devices. The CPU can use its direct connection to memory while at the same time performing high speed I/O to video or other devices.
 
That's why A64 chipsets use a 1 chip package. They don't use a north and south, they only have 1 seperate chip.
 
PC eye said:
As usual worng again! The memory controller is integrated not a separate entity as this 2004 article goes into a four page lengthy explaination on. http://www.silentpcreview.com/article169-page1.html
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You lose it sometimes dont you, theres no memory controller on the northbridge of the motherboard of a Athlon 64, its on the CPU!

From your own page

The Athlon 64 has completely bypassed this mechanism and placed the memory controller directly on the CPU. The CPU itself has a direct, high-speed connection to the RAM.
 
StrangleHold said:
theres no memory controller on the northbridge of the motherboard of a Athlon 64, its on the CPU!
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There you go again contradicting yourself. The northbridge still has it's own memory controller. The changes made were integrating a separate memory controller into the cpu. That gives the cpu a faster access to memory and video. The northbridge/southbridge chipsets are still needed for things like ide/sata/floppy controllers as well as other onboard items.
 
Ok so what im hearing is the northbridge does more then just communicate with the cpu and memory? Thats all i really needed to know. But i thought it was the southbridge that did the communicating with the optical drives and hard drives?
 
There you go again contradicting yourself. The northbridge still has it's own memory controller. The changes made were integrating a separate memory controller into the cpu. That gives the cpu a faster access to memory and video.
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It does? Where did you hear that? There's only 1 memory controller in an A64 system. The onboard memory controller has less latencies than if it was in the northbridge.
Ok so what im hearing is the northbridge does more then just communicate with the cpu and memory? Thats all i really needed to know. But i thought it was the southbridge that did the communicating with the optical drives and hard drives?
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The northbridge handles all the IO stuff on single chip chipsets.
 
Dual_Corex2 said:
Ok so what im hearing is the northbridge does more then just communicate with the cpu and memory? Thats all i really needed to know. But i thought it was the southbridge that did the communicating with the optical drives and hard drives?
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It controls the I/O, the bus speeds for the PCI,ISA,AGP,PCIe, but not the bus for the CPU, The CPU talks direct to the Cards in the PCI,AGP and PCIe through the Hyper Transport lanes bypassing the northbridge chip and the memory controller is intergrated into the CPU
 
PC eye said:
There you go again contradicting yourself. The northbridge still has it's own memory controller. The changes made were integrating a separate memory controller into the cpu. That gives the cpu a faster access to memory and video. The northbridge/southbridge chipsets are still needed for things like ide/sata/floppy controllers as well as other onboard items.
Click to expand...

I think theres something really wrong with you!

This is even from the link you gave

The Athlon 64 has completely bypassed this mechanism and placed the memory controller directly on the CPU. The CPU itself has a direct, high-speed connection to the RAM.
 
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The CPU talks direct to the Cards in the PCI,AGP and PCIe through the Hyper Transport lanes bypassing the northbridge chip
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The communication to the card bus (PCI/PCIe/AGP) is through the link to the northbridge. In the case where an A64 platform has a north and southbridge the northbridge just handles the AGP/PCIe 16x bus as well as communication to the southbridge and the southbridge handles the rest of the IO.
 
Yea thats true but the chipset uses HyperTransport to connect its north and south bridges.

The Direct Connect Architecture is the I/O architecture of the Athlon64 and Opteron microprocessors from AMD. It consists of the combination of three elements:
  • The microprocessor is directly connected to DRAM memory through an integrated memory controller.
  • The microprocessor is directly connected through a natively implemented HyperTransport to a high performance I/O subsystem.
  • The microprocessor is directly connected to other CPUs through a proprietary extension running on top of two additional natively implemented HyperTransport interfaces allowing support of a cache-coherent Non-Uniform Memory Access multi-CPU memory access protocol and Symmetric multiprocessing..
 
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