And just what did they use to determine just what frequency was being seen? Where was there any mention of a hardware not software method for determing all that? For any accurate readings you would need a frequency counter with an led or lcd display hard wired into the memory bus on the board itself.
http://hem.passagen.se/communication/freqcount.html
PCeye its pretty common knowledge since the AM2 was released that any odd X AM2 Athlons do not run the memory at full speed. You can try to twist the fact by posting nonsence like that but it does not change the fact that your wrong. Its no wonder you get so many things wrong because you just spit in the face of facts, double talk, twist, mislead. You will go to any lengths just not to admit you wrong. I am not going to post anymore on this (its pointless)
Some quirks of AMD's DDR2 memory support
So. Get this. On Socket AM2 Athlon 64 systems, the clock speed of system memory is derived from the CPU's clock frequency. That makes sense, since the memory controller lives onboard the CPU. The memory clock runs at some fraction of the CPU clock speed, and the ratio of CPU clock to memory clock is determined by a divisor. Yet only whole-number divisors are available on these chips, and that limits the available memory clock speeds.
Let's illustrate. Take, for example, the Athlon 64 X2 4800+ running at 2.4 GHz—or 2400 MHz. If you want to run DDR2 memory at an effective speed of 800 MHz, you can use a divisor of six. 2400 MHz divided by six is 400 MHz, and a base clock of 400 MHz results in DDR2 memory humming along nicely at an effective 800 MHz. Similarly, a divisor of nine will produce a base memory clock of 266.6 MHz, perfect for DDR2-533 memory.
But what if you want to run DDR2-667 memory? You could use a divisor of seven to get to 343 MHz, or effectively 686 MHz once DDR2's clock-doubling does its magic, or you could try a divisor of eight, to hit 300/600 MHz memory clocks. Getting to 667 MHz is impossible, though.
AMD's answer to this problem is to get as close to the JEDEC-specified memory clock frequency without going over and call it a day. Not kidding. Our Athlon 64 X2 4800+ would run DDR2-667 memory at 600 MHz.
Try another example. The Athlon 64 X2 4200+ flips bits at 2.2 GHz. With whole-number divisors, it can set its memory clock speeds to, effectively, 489 MHz for DDR2-533, 628 MHz for DDR2-667, and 733 MHz for DDR2-800. That's it. None of 'em will run at their full potential.
I haven't consulted with the appropriate JEDEC committee, but I believe the technical term for an implementation like this one is "half-assed." Yes, it seems to work well enough, and no, underclocking memory isn't likely to be an egregious violation of the spec. We've already acknowledged that AMD's approach to memory performance focused much more on latency than bandwidth, and any overclocker knows we can probably squeeze tighter timings (and thus lower latencies) out of that underclocked RAM with a bit of tweaking. Still, I find it hard to believe AMD's new processors actually handle memory clock speeds in this way. This quirk will likely have odd implications for the relative performance of different speed grades of Socket AM2 processors in tasks particularly sensitive to memory bandwidth. System power consumption will also be affected, I suppose.
http://techreport.com/articles.x/10073/2