An embedded system is designed that can simultaneously digitize and store 4 channels of analogue signal. Each analogue signal can be digitized into 4096 levels at a rate of 56 KHz. A program containing 200 instructions can be used to compress each of the digitized data. Assume that the average bit length of the instruction is 32. The real-time operating system codes and other application programs are of 4 Kbytes.
Microcontroller A
Clock rate (MHz) 8
Internal bus width16
On-chip ROM 8 Kbytes
On-chip RAM 2 Kbytes
Number of pipeline stages 4
Number of superscalar units 2
Number of interrupt pins 1
Microcontroller A
Clock rate (MHz) 12
Internal bus width16
On-chip ROM 4 Kbytes
On-chip RAM 2 Kbytes
Number of pipeline stages 1
Number of superscalar units 1
Number of interrupt pins 1
For the two microcontrollers as shown in above, which one should be selected for the embedded system that can execute the program for real-time data compression. Both microcontrollers can execute one instruction in the pipeline in one clock cycle. Show all the calculations and the reasons to justify your choice. What are the assumptions you have made in your calculations?
You are required to implement a timer for the embedded system. It contains both hardware and software. The hardware part contains an 8-bit up counter, which is incremented once for every instruction executed by the microcontroller selected in previous question. Determine the resolution and range of the timer. Suggest how you will modify the timer in order to extend the range of measurement. Describe one possible drawback of your modification.
The I/O devices can get the attention of the microcontroller by using interrupt. For the microcontroller selected in part (b), there are two I/O devices connected to the interrupt request input pin. It is known that each device will activate the interrupt request signal for 4 clock cycles. There is a case that the second device will activate the interrupt request signal 2 clock cycles after the interrupt of the first device. Assume that the interrupt request input is programmable (level-sensitive or edge sensitive). Suggest how you would like to program this input pin. Explain why.
Microcontroller A
Clock rate (MHz) 8
Internal bus width16
On-chip ROM 8 Kbytes
On-chip RAM 2 Kbytes
Number of pipeline stages 4
Number of superscalar units 2
Number of interrupt pins 1
Microcontroller A
Clock rate (MHz) 12
Internal bus width16
On-chip ROM 4 Kbytes
On-chip RAM 2 Kbytes
Number of pipeline stages 1
Number of superscalar units 1
Number of interrupt pins 1
For the two microcontrollers as shown in above, which one should be selected for the embedded system that can execute the program for real-time data compression. Both microcontrollers can execute one instruction in the pipeline in one clock cycle. Show all the calculations and the reasons to justify your choice. What are the assumptions you have made in your calculations?
You are required to implement a timer for the embedded system. It contains both hardware and software. The hardware part contains an 8-bit up counter, which is incremented once for every instruction executed by the microcontroller selected in previous question. Determine the resolution and range of the timer. Suggest how you will modify the timer in order to extend the range of measurement. Describe one possible drawback of your modification.
The I/O devices can get the attention of the microcontroller by using interrupt. For the microcontroller selected in part (b), there are two I/O devices connected to the interrupt request input pin. It is known that each device will activate the interrupt request signal for 4 clock cycles. There is a case that the second device will activate the interrupt request signal 2 clock cycles after the interrupt of the first device. Assume that the interrupt request input is programmable (level-sensitive or edge sensitive). Suggest how you would like to program this input pin. Explain why.
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