How do Intel systems know how much to increment the instruction pointer?

[jj1984]

OK, so it's obvious to me, through reading the Intel "bible", that Intel systems are definitely not RISC systems.

I suppose, in my limited experience, that one aspect of CISC systems is complicated opcode schemes.

That is, CISC systems based on n-bit architectures don't necessarily operate on a set of purely n-bit opcodes.

For example, modern Intel 64-bit processors operate on opcodes that may be anywhere from one byte long to 15 bytes long.

My question is: how do Intel systems know that the next instruction is n bytes long and that the instruction pointer register should be adjusted accordingly?

 

[Cromewell]

The by inscrutions themselves.

An x86-64 instruction may be at most 15 bytes in length. It consists of the following components in the given order, where the prefixes are at the least-significant (lowest) address in memory:

• Legacy prefixes (1-4 bytes, optional)
• Opcode with prefixes (1-4 bytes, required)
• ModR/M (1 byte, if required)
• SIB (1 byte, if required)
• Displacement (1, 2, 4 or 8 bytes, if required)
• Immediate (1, 2, 4 or 8 bytes, if required)

 

[jj1984]

Thanks.