You don't get it, these are 1337 i7 push pins.



So? They wouldn't do this unless it had a positive impact on performance. L3 is still a lot faster than RAM, they're reducing the L2 cache sizes because there's really no point in having a large L2 cache because larger cache=slower cache OR higher miss rate (either affects the performance negatively). It's a lot better, performance-wise, to keep the low levels of cache small so that they can operate efficiently, and add a new level of cache that acts as a high-speed "buffer" between L2 and RAM. Phenoms implemented L3 cache, along with some other advanced memory features, and while overall performance of those things turned out to be pretty poor their memory performance is more than twice as good as that of comparable Intel Quads according to several benchies I've seen.its going to have a much smaller 256kb L2 cache, and a much slower 8mb L3 cache.
If you didn't know they are enabling SLI on the X58 Intel chipset. I will be upgrading when this comes out.
