Timing will effect the amount of data the CPU receives in a certain time regardless of the mhz. its running at.
I,m going to go stupid noob and use cars. Cars on two different roads. All going 30mph. If the red lights last a fraction of a second longer on the first road, then there will be more cars get to the other end on the second road faster. Doesnt matter if all cars were traveling at 30mph.
what type of cars are on the road...
Some accelerate faster....say there was like 15 yugos and 1 lamborghini...
Like tyttebovs said, the internal clockspeed doesn't matter (since it's half of the external speed and that can't be changed). The memory bus clockspeed is still the same as FSB clockspeed when the divider is set to 1:1. DDRn RAM is rated at double the external clockspeed, or the bus speed; hence, the rating of Dual Data Rate RAM should be half of the rating of the Quad Data rate FSB. Since I'm a nice boy P), I bolded the incorrect part for you; as I said, the external memory clock is the one that runs in sync with the FSB when the divider is set to 1:1. The internal clock speed, in your example, would be the half of the external clock, or 133MHz, whereas you seem to think that when the divider is 1:1 the FSB the internal clockspeed of the RAM will be synced with the FSB - this is incorect.
From wikipedia: http://en.wikipedia.org/wiki/Pumping_(computer_systems)
The SPD doesn't list the internal/chip speed. It lists the speed in which the ram module talks to the outside world.
The internal speed is only relevant, if you look at how the module is constructed. What is relevant is how the bus between the module and memory controller works. And this bus is double pumped.
Also remember that the latency numbers are relative to how fast the bus is running. A "5" takes longer at 200Mhz than it does at 400Mhz
Its not, its multiplied by 2. The memory is running at 400mhz. You can say 800mhz because of the memory being DDR itself but theoredically its running at 400mhz.
You have: command(s), data on the bus, command(s), data on the bus, command(s), ...
So the delay between data on the bus affects how much data you get through
But why would the BIOS say memory multiplier: 4
I was looking around the subject and here is what THG states
"A 3.73 GHz Pentium 4 Extreme Edition processor was our chosen chip, because it works with the system clock set to 266 MHz to produce FSB1066; with a 1:1 FSB/memory ratio, that also means the memory runs at DDR2-1066."
This would mean my statement was true and that in a 1:1 ratio a 266 chip is not DDR2-533 (which when divided by 2 would equal 266) but rather DDR2-1066."
The P4EEs are also quad-pumped so they are no different than a Core2 in the situation.
CPU-Z of DDR2-1066
it shows that the frequency is roughly 1066/4
I dont know any other way to explain it to you. The Screenshot looks like a stick of 512mb. DDR2 533 overclocked a couple of mhz. Memory is not Quad pumped.
No, just because something it double or quad pumped does not mean that the bus runs at that mhz. If we are talking about a (1:1). If you have a 266 FSB quad pumped/1066 the bus is still running at 266. So a 1:1 with memory would be running DDR2 533 because both base clocks are running at 266.
Look at it this way: if the (double pumped) bus between the memory controller and ram is running at 266 (533) Mhz, how in earth will you transfer data from a ram module running at 533 (1024) Mhz?