2048Megabytes
Active Member
Found this information on DDR2 memory on the Internet:
"Since DDR already transfers data on both the rising and falling edges of a clock cycle, how does DDR2 double the bandwidth yet again? The answer lies in the I/O buffer frequency, which is doubled with DDR2. The memory controller in our systems only deal with the I/O buffer on the memory chip. To double the data from the memory array to the I/O buffer, DDR2 utilizes a 4-bit prefetch as opposed to the 2-bit prefetch with DDR RAM. This means that 4 bits of data are moved from the memory array to the I/O buffer per data line each core clock cycle."
So I am a little baffled. The memory controller hub is in the north bridge chip on the motherboard. Where is the memory array? (Is it also in the northbridge chip?)
The input/output buffer is in the RAM modules also correct?
"Since DDR already transfers data on both the rising and falling edges of a clock cycle, how does DDR2 double the bandwidth yet again? The answer lies in the I/O buffer frequency, which is doubled with DDR2. The memory controller in our systems only deal with the I/O buffer on the memory chip. To double the data from the memory array to the I/O buffer, DDR2 utilizes a 4-bit prefetch as opposed to the 2-bit prefetch with DDR RAM. This means that 4 bits of data are moved from the memory array to the I/O buffer per data line each core clock cycle."
So I am a little baffled. The memory controller hub is in the north bridge chip on the motherboard. Where is the memory array? (Is it also in the northbridge chip?)
The input/output buffer is in the RAM modules also correct?