Okedokey
Well-Known Member
A lot of the issue is the L1 and L2 cache latency. As Strangle pointed out, the improvements to the scheduler are only going to see in reality around 4% improvement. This is not really detectable. Even 10%. The problem here is that each module has only 1 floating point unit for every 2 integer units, thereby relying on large caches with larger TDP and latencies. Thus the issue. Really, 2billion transistors should see more performance. This is a workstation CPU, not a desktop CPU. A bit lame really considering the hype.